1. Field of the Invention
This invention relates generally to output buffer circuits and, more particularly, to a controlled output impedance buffer circuit using complementary metal-oxide semiconductor (CMOS) technology.
2. Description of the Related Art
In integrated circuits, such as, for example, microprocessor and memory circuits, digital signals may be transmitted relatively long distances over transmission lines. A transmission line may be a bus, a printed circuit board trace, or any other similar structure. Typically, a transmission line has a characteristic impedance of 50 to 75 ohms.
Output buffer circuits are used to drive (i.e., send data over) transmission lines. Like transmission lines, output buffer circuits will have an impedance. The impedance of a typical output buffer circuit is dependent upon the components included in the circuit. Problems occur when the output buffer circuit has an impedance that does not match the impedance of the transmission line. For example, the digital signal may be reflected back and forth between the output buffer circuit and the logic at the receiving end (also known as the far end) of the transmission line. These undesirable reflections result in reduced noise immunity and increase the time for the signal to become, and remain, valid at the far end of the transmission line.
FIG. 1. illustrates a prior art technique attempting to remedy impedance mismatches between output buffer circuits 10 and transmission lines. The circuit 10 includes an inverter 12, a NAND gate 14, a NOR gate 16 and two complementary metal-oxide semiconductor (CMOS) transistors 18, 20. It is well known in the art that the amount of current a CMOS transistor 18, 20 can carry is proportional to W/L (where W is the width of the transistor 18, 20 and L is the gate length of the transistor 18, 20). Accordingly, the W/L ratio of a transistor 18, 20 controls the current flowing through it, which also controls its impedance. For example, by decreasing the width of the transistor 18, 20, the current flowing through it will decrease. Accordingly, the impedance of the transistor 18, 20 will go up. Conversely, increasing the width of the transistor 18, 20 increases the current it can carry, which accordingly, decreases its impedance.
The first transistor 18 is a p-channel transistor having its source terminal connected to the power supply voltage V.sub.DD. The first transistor 18 has its drain terminal connected to node 22 and is used to pull-up the output Z of the circuit 10. The second transistor 20 is an n-channel transistor having its source terminal connected to a nominally ground voltage V.sub.SS. The second transistor 20 has its drain terminal connected to node 22 and is used to pull-down the output Z of the circuit. The input to the NAND gate 14 is the input signal A and an input enable signal EN. The output P of the NAND gate 14 is connected to the gate of the first transistor 18. The input to the inverter 12 is the input enable signal EN. The output of the inverter 12 is an inverted input enable signal STN. The input to the NOR gate 16 is the input signal A and the inverted input enable signal STN. The output of the NOR gate 16 is connected to the gate of the second transistor 20.
The output Z of the circuit 10 is determined at node 22. When the input enable signal EN is high, the output Z follows the input signal A. That is, if the input signal A is high, the second transistor 20 is off and the first transistor 18 is turned on pulling up the output Z. Accordingly, if the input signal A is low, the first transistor is off and the second transistor 20 is turned on pulling down the output Z. When the input enable signal EN is low, both transistors 18, 20 are off causing the output impedance to be infinite.
Accordingly, if the width of the two transistors 18, 20 are carefully sized, and the manufacturing process, operating temperature and power supply voltage V.sub.DD are properly controlled, it is possible that each transistor 18, 20 can have an impedance in the linear region that matches the transmission line's impedance when they are switched on. Unfortunately, CMOS transistors 18, 20 have very non-linear I-V characteristics. Referring now to FIG. 2a, it can be seen that CMOS transistors 18, 20 have a very small linear region 30 and a much larger non-linear region 32.
The slope of these regions 30, 32 represent the conductance (defined as 1/impedance) of the transistors 18, 20. The typical linear region 30 spans only a few tenths of a volt. Therefore, when a drain-to-source voltage on either transistor 18, 20 becomes greater than a few tenths of a volt, the output impedance of the circuit 10 increases dramatically regardless of the width of the transistors 18, 20. In addition, the output impedance will also be altered by any variations in the manufacturing process, operating temperature and power supply voltage V.sub.DD.
One solution to the problem of non-linearity in the output buffer circuit 10 is to effectively replace the non-linear elements with linear elements. FIG. 3 illustrates an output buffer circuit 40 incorporating two resistors 42, 44 to provide linearity and, therefore, a more stable impedance matching characteristic. Referring now to FIG. 2b, it can be seen that typical resistors 42, 44 have a linear region 34 that spans the entire voltage range. The slope of this region 34 represents the conductance of the resistors 42, 44. Therefore, regardless of the output voltage across the resistors 42, 44, their impedance will not change dramatically as in the case of the transistors 18, 20. Accordingly, the output impedance of the circuit 40 will not change dramatically either, as long as the resistor's impedance is significantly greater than the transistor's impedance.
Referring again to FIG. 3, the first resistor 42 is connected between the drain terminal of the first transistor 18 and node 22. Therefore, the series combination of the first resistor 42 and the first transistor 18 is used to pull-up the output Z. The second resistor 44 is connected between the drain terminal of the second transistor 20 and node 22. Therefore, the series combination of the second resistor 44 and the second transistor 20 is used to pull-down the output Z.
If the two resistors 42, 44 and the width of the two transistors 18, 20 are sized such that each resistor 42, 44 has a much higher impedance than each transistor 18, 20, then the non-linearity problem of circuit 10 (FIG. 1) is overcome. FIG. 4 illustrates the resultant linearity of circuit 40 in comparison to the non-linearity of circuit 10 in relation to the output voltage and resultant impedance of the two circuits 10, 40. The output impedance of the output buffer circuit 10 vs. its output voltage is illustrated by line 50. The output impedance of the output buffer circuit 40 vs. its output voltage is illustrated by line 52. At the two extremes of the output voltage (that is, 0 and 3.3 volts) the output impedance of both circuits is approximately the impedance of the transmission line (in this example, 50 ohms). However, the output impedance of the circuit 10 goes well over 1000 ohms in the mid range of the output voltage, while the impedance of the circuit 40 remains within 10% of 50 ohms through out the entire voltage range. Therefore, due to the linearity of the circuit 40, variations in the output voltage would not dramatically alter the output impedance of the circuit 40.
The impedance of the transistors 18, 20 and the resistors 42, 44, however, can be effected by variations in the manufacturing process. It is known that the manufacturing process will have some known degree of variation. Worst-case slow (WCS), a condition where the impedance is at a maximum (expected impedance plus the known maximum variation), is caused by an increase in impedance of the transistors 18, 20 and resistors 42, 44 during the manufacturing of these parts. Worst-case fast (WCF), a condition where the impedance is at a minimum (expected impedance minus the known maximum variation), is caused by a decrease in impedance of the transistors 18, 20 and resistors 42, 44 during the manufacturing of these parts. WCF, WCS and intermediate impedance conditions are caused by variations in sheet impedance (i.e., impedance of the materials used) which are very difficult to control. In addition, operating temperature and power supply voltage V.sub.DD variations will also cause the output impedance of the circuit 40 to mismatch the impedance of the transmission line.
Therefore, although the output buffer circuit 40 is a vast improvement over the circuit 10 illustrated in FIG. 1, there is still a need and desire to properly adjust the output impedance of an output buffer circuit 40 to overcome any of the aforementioned variations.